This invention relates to digital signal processing apparatus in general, and more particularly, to a processing register for use in digital signal processing systems.
It has long been recognized that many future products in the telecommunications field would operate based upon digital signal processing. By digitally processing data such as voice, video, radar, sonar and other signals, one can achieve greater reliability and lower cost as digital circuits are, in most cases, easier to integrate and produce than their analog counterparts.
In general, digital signal processing is based, upon multiplication, summation, subtraction and storage of digital data and by performing these functions upon digital signals many useful devices can be implemented in a telecommunications system. The prior art is replete with a number of patents and technical articles relating to digital signal processing techniques and systems employing such techniques.
A powerful combination for performing digital signal processing is the combination of a high speed multiplier operating in conjunction with a processing register. The function of the multiplier is to perform multiplication and accumulation of data applied to its inputs. The multiplier may be a programmable device and may operate on digital data streams at the inputs to provide a sum of products. There are many examples of multipliers in the prior art.
The processing register is a device which can perform the remaining arithmetic operations such as summation, subtraction and delay.
The prior art attempted to implement processing register construction by the use of a large number of integrated circuit chips as well as custom components which varied and changed according to the application.
This leads to great difficulty in implementing digital processing systems in regard to cost, reliability and power consumption.
To provide this utility and to be able to accomodate these functions, the processing register must be versatile and may provide a number of different operating modes to accomodate a host of diverse applications. It should also be simple to operate and use.
These criterion and others dictate that the structure and architecture of such a unit be amenable to providing a wide host of functions and that the unit might be capable of operation in various modes to enable the system designer to employ the register as desired.
Particularly useful functions for the combination of a processing register and a multiplier is the utilization of these devices to implement digital filters and discrete Fourier transforms. With the processing registers versatility discrete Fourier transforms, Finite Impulse Response Filters (FIR filters), or Infinite Impulse Response Filters (IIF filters) are examples of digital signal processing configurations which can be implemented.
This utility enables the digital system engineer to implement various operations and devices such as digital hybrids, adaptive equalizer systems, echo cancellation systems, stand alone signaling systems, digital filters, spectrum analysis, correlation, speech analysis and a host of other functions.
It is therefore an object of the present invention to provide an improved processing register for use in digital signal processing which is capable of providing the ability to operate in a wide number of applications for the selective processing of digital signals.